1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to an apparatus for and method of polishing.
2. Discussion of Related Art
During Integrated Circuit (IC) manufacturing, devices are formed by deposition, patterning, and selective removal of various layers on a semiconductor substrate, such as a Silicon wafer. For example, a conductive structure, such as an interconnect, is formed from a metallic layer while an insulative structure, such as isolation for the interconnect, is formed from a dielectric layer.
Planarization of the surface of a wafer is necessary in order to achieve an adequate depth of focus (DOF) for patterning by lithography. The layers on a wafer may be planarized by chemical mechanical polishing (CMP). The process of CMP combines chemical etching with mechanical lapping. For example, CMP may involve polishing of a metal that has been deposited on a barrier layer over insulation. The metal is relatively soft while the barrier layer is relatively hard.
Polish selectivity may be changed by adjusting the polish rates of different materials. It is desirable to achieve a low polish selectivity between the metal and the barrier layer to avoid dishing. It is also desirable to achieve a high polish selectivity between the metal and the insulation to avoid erosion. The high selectivity of the metal over the insulation allows the insulation to serve as a polish stop layer. Polish selectivity may be optimized by changing the properties of the polish pad and the composition of the polish slurry.
In advanced IC devices, the insulation is formed from a material with a low dielectric constant (low-k) rather than with Silicon Dioxide. However, a high selectivity between the metal and the low-k material becomes difficult to achieve since the low-k material usually has poor mechanical properties.
Thus, what is needed is an apparatus for and a method of improving the planarization of a surface layer.